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DS90UR906Q - 5 - 65 MHz 24-bit Color FPD-Link Serializer/Deserializer

Download the DS90UR906Q datasheet PDF. This datasheet also covers the DS90UR905Q variant, as both devices belong to the same 5 - 65 mhz 24-bit color fpd-link serializer/deserializer family and are provided as variant models within a single manufacturer datasheet.

General Description

The DS90UR905Q/906Q chipset translates a parallel RGB Video Interface into a high-speed serialized interface over a single pair.

Key Features

  • and receiver equalization. EMI is minimized by the use of low voltage differential signaling, receiver drive strength control, and spread spectrum clocking compatibility. The Des may be configured to generate Spread Spectrum Clock and Data on its parallel outputs. The DS90UR905Q (Ser) is offered in a 48-pin LLP and the DS90UR906Q (Des) is offered in a 60-pin LLP package. They are specified over the automotive AEC-Q100 grade 2 temperature range of -40°C to +105°C. Features.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DS90UR905Q_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DS90UR905Q/DS90UR906Q 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer May 26, 2010 DS90UR905Q/DS90UR906Q 5 - 65 MHz 24-bit Color FPD-Link II Serializer and Deserializer General Description The DS90UR905Q/906Q chipset translates a parallel RGB Video Interface into a high-speed serialized interface over a single pair. This serial bus scheme greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced decoding is used to support AC-coupled interconnects. The DS90UR905Q Ser (serializer) embeds the clock, balances the data payload, and level shifts the signals to highspeed low voltage differential signaling.