GENERAL DESCRIPTION
To minimize bus loading the driver outputs and receiver inputs are internally connected. The device also features flow through which allows easy PCB routing for short stubs between the bus pins and the connector. The driver has 10 mA drive capability, allowing it to drive heavily loaded backplanes, with impedance as low as 27 Ohms. The driver translates between TTL levels (single-ended) to Low Voltage Differential Signaling levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition the differential signaling provides common mode noise rejection of ± 1V. The receiver threshold is ± 100mV over a ± 1V common mode range and translates the low voltage differential levels to standard (CMOS/TTL) levels. FEATURES
n n n n n n n n n n n n Bus LVDS Signaling (BLVDS) Designed for Double Termination APPLICATIONS
Balanced Output Impedance Lite Bus Loading 5pF typical Glitch free power up/down (Driver disabled) 3.3V or 5.0V Operation...
National Semiconductor
