DS92LV010A Datasheet | Texas Instruments

.ti. SNLS007E - MAY 1998 - REVISED APRIL 2013 DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver Check for Samples: DS92LV010A Features - 2 Bus LVDS Signaling (BLVDS) - Designed for Double Termination Applications - Balanced Output Impedance - Lite Bus Loading 5p F Typical - Glitch Free Power Up/Down (Driver Disabled) - 3.3V or 5.0V Operation - ±1V mon Mode Range - ±100m V Receiver Sensitivity - High Signaling Rate Capability (Above 100 Mbps) - Low Power CMOS Design - Product Offered in 8 Lead SOIC Package - Industrial Temperature Range Operation DESCRIPTION The DS92LV010A is one in a series of transceivers designed specifically for the high speed, low power proprietary bus backplane interfaces. The device operates from a single 3.3V or 5.0V power supply and includes one differential line driver and one receiver. To minimize bus loading the driver outputs and receiver inputs are internally connected. The logic interface provides maximum flexibility as 4 separate lines are provided (DIN, DE, RE, and ROUT). The device also Features flow through which allows easy PCB routing for short stubs between the bus pins and the connector. The driver has 10 m A drive capability, allowing it to drive heavily loaded backplanes, with impedance as low as 27 Ohms. The driver translates between TTL levels (singleended) to Low Voltage Differential Signaling levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition the differential signaling provides mon mode noise rejection of ±1V. The receiver threshold is ±100m V over a ±1V mon mode range and translates the low voltage differential levels to standard (CMOS/TTL) levels. CONNECTION DIAGRAM BLOCK DIAGRAM Figure 1. SOIC Package See Package Number D0008A Figure 2. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at...