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DS92LV010A - Bus LVDS 3.3/5.0V Single Transceiver

General Description

The DS92LV010A is one in a series of transceivers designed specifically for the high speed, low power proprietary bus backplane interfaces.

The device operates from a single 3.3V or 5.0V power supply and includes one differential line driver and one receiver.

Key Features

  • 1.
  • 2 Bus LVDS Signaling (BLVDS).
  • Designed for Double Termination.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DS92LV010A www.ti.com SNLS007E – MAY 1998 – REVISED APRIL 2013 DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver Check for Samples: DS92LV010A FEATURES 1 •2 Bus LVDS Signaling (BLVDS) • Designed for Double Termination Applications • Balanced Output Impedance • Lite Bus Loading 5pF Typical • Glitch Free Power Up/Down (Driver Disabled) • 3.3V or 5.0V Operation • ±1V Common Mode Range • ±100mV Receiver Sensitivity • High Signaling Rate Capability (Above 100 Mbps) • Low Power CMOS Design • Product Offered in 8 Lead SOIC Package • Industrial Temperature Range Operation DESCRIPTION The DS92LV010A is one in a series of transceivers designed specifically for the high speed, low power proprietary bus backplane interfaces. The device operates from a single 3.3V or 5.