DS92LV010AEP Datasheet | National Semiconductor

DS92LV010AEP Bus LVDS 3.3/5.0V Single Transceiver .. OBSOLETE June 15, 2009 Bus LVDS 3.3/5.0V Single Transceiver General Description The DS92LV010AEP is one in a series of transceivers designed specifically for the high speed, low power proprietary bus backplane interfaces. The device operates from a single 3.3V or 5.0V power supply and includes one differential line driver and one receiver. To minimize bus loading the driver outputs and receiver inputs are internally connected. The logic interface provides maximum flexibility as 4 separate lines are provided (DIN, DE, RE, and ROUT). The device also Features flow through which allows easy PCB routing for short stubs between the bus pins and the connector. The driver has 10 m A drive capability, allowing it to drive heavily loaded backplanes, with impedance as low as 27 Ohms. The driver translates between TTL levels (single-ended) to Low Voltage Differential Signaling levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition the differential signaling provides mon mode noise rejection of ±1V. The receiver threshold is ±100m V over a ±1V mon mode range and translates the low voltage differential levels to standard (CMOS/TTL) levels. ENHANCED PLASTIC - - - - - - Extended Temperature Performance of -40°C to +85°C Baseline Control - Single Fab & Assembly Site Process Change Notification (PCN) Qualification & Reliability Data Solder (Pb Sn) Lead Finish is standard Enhanced Diminishing Manufacturing Sources (DMS) Support Features - - - - - - - - - - - Bus LVDS Signaling (BLVDS) Designed for Double Termination Applications Balanced Output Impedance Lite Bus Loading 5p F typical Glitch free power up/down (Driver disabled) 3.3V or 5.0V Operation ±1V mon Mode Range ±100m V Receiver Sensitivity High Signaling Rate Capability (above 100 Mbps) Low Power CMOS design Product offered in 8 lead SOIC package Applications Selected Military...