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DS92LV18 - 18-Bit Bus LVDS Serializer/Deserializer

General Description

The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18

bit parallel bus into a BLVDS serial stream with embedded clock information.

Key Features

  • n 15.
  • 66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps full duplex throughput) n Independent transmitter and receiver operation with separate clock, enable, and power down pins n Hot plug protection (power up high impedance) and synchronization (receiver locks to random data) n Wide ± 5% reference clock frequency tolerance for easy system design using locally-generated clocks n Line and local loopback modes n Robust BLVDS serial transmission across backplanes and cables for low EMI n.

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Part Number Description Manufacturer
DS92LV18 18-Bit Bus LVDS Serializer/Deserializer Texas Instruments

Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
DS92LV1021 16-40 MHz 10 Bit Bus LVDS Serializer/Deserializer
DS92LV1021A 16-40 MHz 10 Bit Bus LVDS Serializer
DS92LV1023 40-66 MHz 10 Bit Bus LVDS Serializer/Deserializer
DS92LV1212 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer
DS92LV1224 40-66 MHz 10 Bit Bus LVDS Serializer/Deserializer
DS92LV1260 Six Channel 10 Bit BLVDS Deserializer
DS92LV16 16-Bit Bus LVDS Serializer/Deserializer
DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver
DS92LV010AEP Bus LVDS 3.3/5.0V Single Transceiver
DS92LV040A 4 Channel Bus LVDS Transceiver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz October 2003 DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz General Description The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. This SERDES pair includes built-in system and device test capability.