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DS9622 - Dual Line Receiver

General Description

The DS9622 is a dual line receiver designed to discriminate a worst case logic swing of 2V from a ± 10V common mode noise signal or ground shift.

A 1.5V threshold is built into the differential amplifier to offer a TTL compatible threshold voltage and maximum noise immunity.

Key Features

  • n n n n n n n n TTL compatible threshold voltage Input terminating resistors Choice of output state with inputs open TTL compatible output High common mode Wired-OR capability Enable inputs Logic compatible supply voltages Connection Diagram 14.
  • Lead DIP DS009760-2 Top View For Complete Military 883 Specifications, see RETS Datasheet. Order Number DS9622ME/883, DS9622MJ/883 or DS9622MW/883 See NS Package Number E20A, J14A or W14B © 1999 National Semiconductor Corporation DS009760 ww.

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Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
DS9627 Dual Line Receiver
DS9615 Dual Differential Line Receiver
DS96172 RS-485/RS-422 Quad Differential Line Drivers
DS96173 RS-485/RS-422 Quad Differential Line Receivers
DS96174 RS-485/RS-422 Quad Differential Line Drivers
DS96175 Quad Differential Line Receivers
DS96176 RS-485/RS-422 Differential Bus Transceiver
DS96176CN RS-485/RS-422 Differential Bus Transceiver
DS96177 RS-485/RS-422 Differential Bus Repeater
DS9636A RS-423 Dual Programmable Slew Rate Line Driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DS9622 Dual Line Receiver October 1993 DS9622 Dual Line Receiver General Description The DS9622 is a dual line receiver designed to discriminate a worst case logic swing of 2V from a ± 10V common mode noise signal or ground shift. A 1.5V threshold is built into the differential amplifier to offer a TTL compatible threshold voltage and maximum noise immunity. The offset is obtained by use of current sources and matched resistors. The DS9622 allows the choice of output states with the input open, without affecting circuit performance by use of S3. A 130Ω terminating resistor is provided at the input of each line receiver. An enable is also provided for each line receiver. The output is TTL compatible.