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FPD87392BXB - +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA)

Download the FPD87392BXB datasheet PDF. This datasheet also covers the FPD variant, as both devices belong to the same +3.3v tft-lcd timing controller with dual lvds inputs/dual rsds outputs for tft-lcd monitor and notebook (sxga/sxga+/uxga) family and are provided as variant models within a single manufacturer datasheet.

General Description

The FPD87392BXB Panel Timing Controller is an integrated FPD-Link + RSDS™ + TFT-LCD Timing Controller.

The logic architecture is implemented using standard and default timing controller functionality based on an Embedded Gate Array.

Key Features

  • n Input frequency range from 25 MHz to 85 MHz n Support display resolutions SXGA (1280x1024), SXGA+ (1400x1050) and UXGA (1600x1200) n Embedded gate array for custom panel timing n RSDS™ (Reduced Swing Differential Signaling) Column Driver bus for low power and reduced EMI n Drives RSDS™ column driver up to 170 Mb/s with an 85 MHz clock n 6 or 8 bit LVDS dual pixel input interface (FPD-Link) n Virtual 8-bit color depth in FRC mode n Flexible RSDS™ data output mapping for Bottom or Top mount n Su.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (FPD-873.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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FPD87392BXB +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS™ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA) July 2004 FPD87392BXB +3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS™ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA) General Description The FPD87392BXB Panel Timing Controller is an integrated FPD-Link + RSDS™ + TFT-LCD Timing Controller. The logic architecture is implemented using standard and default timing controller functionality based on an Embedded Gate Array. The device is reconfigurable to the needs of a specific application by providing user-defined specifications or customer supplied VHDL/Verilog code.