LMK02002 Datasheet | National Semiconductor

LMK02002 Precision Clock Conditioner with Integrated PLL .. PRELIMINARY August 2007 LMK02002 Precision Clock Conditioner with Integrated PLL General Description The LMK02002 precision clock conditioner bines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), and four LVPECL clock output distribution blocks. Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system ponents. The clock conditioner es in a 48-pin LLP package and is footprint patible with other clocking devices in the same family. Features - 20 fs additive jitter - Integrated Integer-N PLL with outstanding normalized - - - - - - phase noise contribution of -224 d Bc/Hz Clock output frequency range of 1 to 800 MHz 4 LVPECL clock outputs Dedicated divider and delay blocks on each clock output Pin patible family of clocking devices 3.15 to 3.45 V operation Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm) Target Applications - - - - - - Data Converter Clocking Networking, SONET/SDH, DSLAM Wireless Infrastructure Medical Test and Measurement Military / Aerospace Functional Block Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation .national. .. Connection Diagram 48-Pin LLP Package Pin Descriptions Pin # 1, 25 2, 7, 14, 15, 17, 18, 20, 21, 23, 24 Pin Name GND NC I/O I I I I O I I O I I O O O O Ground No Connection to these pins Power Supply MICROWIRE Clock Input MICROWIRE Data Input MICROWIRE Latch Enable Input LDO Bypass Global Output Enable Lock Detect and Test Output Global Clock Output...