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LP2994 - DDR Termination Regulator

General Description

The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications (Series Stub Termination Logic) for active termination of DDRSDRAM.

Key Features

  • n n n n n n n Source and sink current Low external component count Independent analog and power rails Linear topology Small package SO-8 Low cost and easy to use Shutdown pin.

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LP2994 DDR Termination Regulator May 2002 LP2994 DDR Termination Regulator General Description The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications (Series Stub Termination Logic) for active termination of DDRSDRAM. The device utilizes an internal operational amplifier to provide linear regulation of VTT without the need for expensive external components. The output stage prevents shoot through while delivering 1.5A continuous current and maintaining excellent load regulation. The LP2994 also incorporates an active low shutdown pin to tri-state the output during Suspend To Ram (STR) states.