MM54HC174 Datasheet | National Semiconductor

Description These edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flip-flops They possess high noise immunity low power and speeds parable to low power Schottky TTL circuits This device contains 6 master-slave flip-flops with a mon clock and mon clear Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input The CLEAR input when low sets all outputs to a low state Each output can drive 10 low power Schottky TTL equivalent loads The MM54HC174 MM74HC174 is functionally as well as pin patible to the 54LS174 74LS174 All inputs are protected from damage due to static discharge by diodes to VCC and ground Connection and Logic Diagrams Features Y Typical propagation delay 16 ns Y Wide operating voltage range 2 - 6V Y Low input...