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MM74C165 - Parallel-Load 8-Bit Shift Register

Datasheet Summary

Description

The MM54C165 MM74C165 functions as an 8-bit parallelload serial shift register Data is loaded into the register independent of the state of the clock(s) when PARALLEL LOAD (PL) is low Shifting is inhibited as long as PL is low Data is sequentially shifted from complementary outputs Q7 and Q7 highest

Features

  • Y Wide supply voltage range Y Guaranteed noise margin Y High noise immunity Y Low power TT.

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Datasheet Details

Part number MM74C165
Manufacturer National Semiconductor
File Size 91.40 KB
Description Parallel-Load 8-Bit Shift Register
Datasheet download datasheet MM74C165 Datasheet
Additional preview pages of the MM74C165 datasheet.

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Full PDF Text Transcription

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MM54C165 MM74C165 Parallel-Load 8-Bit Shift Register December 1992 MM54C165 MM74C165 Parallel-Load 8-Bit Shift Register General Description The MM54C165 MM74C165 functions as an 8-bit parallelload serial shift register Data is loaded into the register independent of the state of the clock(s) when PARALLEL LOAD (PL) is low Shifting is inhibited as long as PL is low Data is sequentially shifted from complementary outputs Q7 and Q7 highest-order bit (P7) first New serial data may be entered via the SERIAL DATA (Ds) input Serial shifting occurs on the rising edge of CLOCK1 or CLOCK2 Clock inputs may be used separately or together for combined clocking from independent sources Either clock input may be used also as an active-low clock enable To prevent double-clocking when a clock input is u
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