Datasheet4U Logo Datasheet4U.com

MM74C95 - 4-Bit Right-Shift Left-Shift Register

Description

This 4-bit shift register is a monolithic complementary MOS (CMOS) integrated circuit composed of four D flip-flops This register will perform right-shift or left-shift operations dependent upon the logical input level to the mode control A number of these registers may be connected in series to for

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
MM74C90 4-Bit Decade Counter 4-Bit Binary Counter Fairchild
MM74C901 Hex Inverting TTL Buffer Fairchild
MM74C901 Hex Inverting TTL / Non-Inverting TTL / Inverting CMOS / Non-Inverting CMOS Buffer National
MM74C902 Hex Non-Inverting TTL Buffer Fairchild Semiconductor
MM74C902 Hex Inverting TTL / Non-Inverting TTL / Inverting CMOS / Non-Inverting CMOS Buffer National

Other Datasheets by National Semiconductor (Texas Instruments)

Part Number Description
MM74C90 4-Bit Decade Counter
MM74C905 12-Bit Successive Approximation Register
MM74C908 Dual CMOS 30V Relay Driver
MM74C910 256 Bit Tri-state Random Access Read/write Memory
MM74C914 Hex Schmitt Trigger

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MM54C95 MM74C95 4-Bit Right-Shift Left-Shift Register February 1988 MM54C95 MM74C95 4-Bit Right-Shift Left-Shift Register General Description This 4-bit shift register is a monolithic complementary MOS (CMOS) integrated circuit composed of four D flip-flops This register will perform right-shift or left-shift operations dependent upon the logical input level to the mode control A number of these registers may be connected in series to form an N-bit right-shift or left-shift register When a logical ‘‘0’’ level is applied to the mode control input the output of each flip-flop is coupled to the D input of the succeeding flip flop Right-shift operation is performed by clocking at the clock 1 input and serial data entered at the serial input clock 2 and parallel inputs A through D are inhibi
Published: |