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MM74HC533 - Octal D-Type Latch

Datasheet Summary

Description

These high speed OCTAL D-TYPE LATCHES utilize advanced silicon-gate CMOS technology They possess the high noise immunity and low power consumption of standard CMOS integrated circuits as well as the ability to drive 15 LS-TTL loads Due to the large output drive capability and the TRI-STATE feature t

Features

  • Y Typical propagation delay 18 ns Y Wide operating voltage range 2 to 6 volts Y Low input current 1 mA maximum Y Low quiescent current 80 mA maximum (74HC Series) Y Compatible with bus-oriented systems Y Output drive capability 15 LS-TTL loads Connection Diagram Dual-In-Line Package Truth Table Output Control L L L H Top View Order Number MM54HC533 or MM74HC533 TL F 5339.
  • 1 Latch Enable G H H L X Data H L X X Output L H Q0 Z H e high level L e low level Q0 e level of output bef.

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MM54HC533 MM74HC533 TRI-STATE Octal D-Type Latch with Inverted Outputs January 1988 MM54HC533 MM74HC533 TRI-STATE Octal D-Type Latch with Inverted Outputs General Description These high speed OCTAL D-TYPE LATCHES utilize advanced silicon-gate CMOS technology They possess the high noise immunity and low power consumption of standard CMOS integrated circuits as well as the ability to drive 15 LS-TTL loads Due to the large output drive capability and the TRI-STATE feature these devices are ideally suited for interfacing with bus lines in a bus organized system When the LATCH ENABLE input is high the data present on the D inputs will appear inverted at the Q outputs When the LATCH ENABLE goes low the inverted data will be retained at the Q outputs until LATCH ENABLE returns high again When
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