PC16550D Datasheet | National Semiconductor

PC16550D Universal Asynchronous Receiver Transmitter with FIFOs June 1995 PC16550D Universal Asynchronous Receiver Transmitter with FIFOs General Description The PC16550D is an improved version of the original 16450 Universal Asynchronous Receiver Transmitter (UART) Functionally identical to the 16450 on powerup (CHARACTER mode) the PC16550D can be put into an alternate mode (FIFO mode) to relieve the CPU of excessive software overhead In this mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes All the logic is on chip to minimize system overhead and maximize system efficiency Two pin functions have been changed to allow signalling of DMA transfers The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM and parallel-to-serial conversion on data characters received from the CPU The CPU can read the plete status of the UART at any time during the functional operation Status information reported includes the type and condition of the transfer operations being performed by the UART as well as any error conditions (parity overrun framing or break interrupt) The UART includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216b1) and producing a 16 c clock for driving the internal transmitter logic Provisions are also included to use this 16 c clock to drive the receiver logic The UART has plete MODEM-control capability and a processor-interrupt system Interrupts can be programmed to the user’s requirements minimizing the puting required to handle the munications link The UART is fabricated using National Semiconductor’s advanced M2CMOS process Can also be reset to 16450 Mode under software control Note This part is patented Features Y Y Y Y Y Capable of running all existing 16450 software Pin for...