PC16550D Datasheet | Texas Instruments

Product Folder Sample & Buy Technical Documents Tools & Software Support & munity SNLS378C - JUNE 1995 - REVISED MAY 2015 PC16550D Universal Asynchronous Receiver/Transmitter With FIFOs 1 Features - 1 Capable of Running All Existing 16450 Software. - Pin for Pin patible With the Existing 16450 Except for CSOUT (24) and NC (29). The Former CSOUT and NC Pins Are TXRDY and RXRDY, Respectively. - After Reset, All Registers Are Identical to the 16450 Register Set. - In the FIFO(1) Mode Transmitter and Receiver Are Each Buffered With 16 Byte FIFO’s to Reduce the Number of Interrupts Presented to the CPU. - Adds or Deletes Standard Asynchronous munication Bits (Start, Stop, and Parity) to or From the Serial Data. - Holding and Shift Registers in the 16450 Mode Eliminate the Need for Precise Synchronization Between the CPU and Serial Data. - Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts. - Programmable Baud Generator Divides Any Input Clock by 1 to (216 - 1) and Generates the 16 × Clock. - Independent Receiver Clock Input. - MODEM Control Functions (CTS, RTS, DSR, DTR, RI, and DCD). - Fully Programmable Serial-Interface Characteristics - 5-, 6-, 7-, or 8-Bit Characters - Even, Odd, or No-Parity Bit Generation and Detection - 1-, 1 1/2-, or 2-Stop Bit Generation - Baud Generation (DC to 1.5 M Baud). - False Start Bit Detection. - plete Status Reporting Capabilities. - TRI-STATE TTL Drive for the Data and Control Buses. - Line Break Generation and...