SCANSTA101
Overview
The SCANSTA101 is designed to function as a test master for a IEEE 1149.1 test system. The minimal requirements to create a tester are a microcomputer (uP, RAM/ROM, clock, etc.), SCANEASE r2.0 software, and a STA101.
- The flexibility will allow it to adapt to any changes that may occur in 1532 and support yet unknown variants. The SCANSTA101 is useful in improving vector throughput when applying serial vectors to system test circuitry and reduces the software overhead that is associated with applying serial patterns with a parallel processor. The SCANSTA101 features a generic Parallel Processor Interface (PPI) which operates by serializing data from the parallel bus for shifting through the chain of 1149.1 compliant components (i.e., scan chain). Writes can be controlled either by wait states or the DTACK line. Handshaking is accomplished with either polling or interrupts. Features
- Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture
- Supported by National’s SCAN Ease (Embedded Application Software Enabler) Software Rev 2.0
- Available as a Silicon Device and Intellectual Property (IP) model for embedding into VLSI devices
- Uses generic, asynchronous processor interface; compatible with a wide range of processors and PCLK frequencies
- 16-bit Data Interface (IP scalable to 32-bit)
- 2Kx32 bit dual-port memory addressing for access by the PPI or the 1149.1 master
- Load-on-the-fly (LotF) and Preload operating modes supported
- On-Board Sequencer allows multi-vector operations such as those required to load data into an FPGA
- On-Board Com
