SCANSTA101 Description
The SCANSTA101 is designed to function as a test master for an IEEE 1149.1 boundary scan test system. It is suitable for use in embedded IEEE 1149.1 applications and as a ponent in a standalone boundary scan tester. The SCANSTA101 is an enhanced version of, and a replacement for, the SCANPSC100.
SCANSTA101 Key Features
- 2 patible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture
- Supported by Texas Instruments' SCAN Ease (SCAN Embedded Application Software Enabler) Software Rev 2.0
- Uses Generic, Asynchronous Processor Interface; patible with a Wide Range of Processors and Processor Clock (PCLK) Frequ
- 16-Bit Data Interface (IP Scalable to 32-bit)
- 2k x 32 Bit Dual-Port Memory
- Load-on-the-Fly (LotF) and Preloaded Vector Operating Modes Supported
- On-Board Sequencer Allows Multi-Vector Operations such as those Required to Load Data Into an FPGA
- On-Board pares Support Test Data In (TDI) Validation Against Preloaded Expected Data
- 32-Bit Linear Feedback Shift Register (LFSR) at the Test Data In (TDI) Port for Signature pression
- State, Shift, and BIST Macros Allow Predetermined Test Mode Select (TMS) Sequences to be Utilized