Texas Instruments SCANSTA101
The SCANSTA101 is designed to function as a test master for an IEEE 1149.1 boundary scan test system. It is suitable for use in embedded IEEE 1149.1 applications and as a component in a standalone boundary scan tester. The SCANSTA101 is an enhanced version of, and a replacement for, the SCANPSC100.| Part No. | SCANSTA101 |
|---|---|
| Datasheet | SCANSTA101 Download |
| Manufacturer |  Texas Instruments |
| Description | Low Voltage IEEE 1149.1 System Test Access Master |
| Buy | Stock & Price |
FEATURES
1●2 Compatible with IEEE Std. 1149.1 (JTAG) Test Access Port and Boundary Scan Architecture
● Supported by Texas Instruments' SCAN Ease (SCAN Embedded Application Software Enabler) Software Rev 2.0
● Uses Generic, Asynchronous Processor Interface; Compatible with a Wide Range of Processors and Processor Clock (PCLK) Frequencies
● 16-Bit Data Interface (IP Scalable to 32-bit)
● 2k x 32 Bit Dual-Port Memory
● Load-on-the-Fly (LotF) and Preloaded Vector Operating Modes Supported
● On-Board Sequencer Allows Multi-Vector Operations such as those Required to Load Data Into an FPGA
● On-Board Compares Support Test Data In (TDI) Validation Against Preloaded Expected Data
● 32-Bit Linear Feedback Shift Register (LFSR) at the Test Data In (TDI) Port for Signature Compression
● State, Shift, and BIST Macros Allow Predetermined Test Mode Select (TMS) Sequences to be Utilized
● Operates at 3.3 V Supply Voltages with 5 V Tolerant I/O
● Outputs Support Power-Down TRI-STATE Mode.
DESCRIPTION
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