74F544 Datasheet | National Semiconductor

Description The ’F544 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow The A outputs are guaranteed to sink 24 m A (20 m A Mil) while the B outputs are rated for 64 m A (48 m A Mil) The ’F544 inverts data in both directions Features 8-bit octal transceiver Back-to-back registers for storage Separate controls for data flow in each direction A outputs sink 24 m A (20 m A Mil) B outputs sink 64 m A (48 m A Mil) 300 mil slim PDIP mercial 74F544SPC Military Package Number N24C Package Description 24-Lead (0 300 Wide) Molded Dual-In-Line 24-Lead Ceramic Dual-In-Line 24-Lead (0 300 Wide) Ceramic Dual-In-Line 24-Lead (0 300 Wide) Molded Small Outline JEDEC 24-Lead Molded Shrink Small Outline EIAJ Type II 24-Lead Cerpack 24-Lead Ceramic Leadless Chip Carrier Type C 54F544DM (Note 2) 54F544SDM (Note 2) 74F544SC (Note 1) 74F544MSA (Note 1) 54F544FM (Note 2) 54F544LM (Note 2) J24A J24F M24B MSA24 W24C E28A Note 1 Devices also available in 13 reel Use suffix e SCX and MSAX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols IEEE IEC TL F 9555 - 2 TL F 9555 - 1 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9555 RRD-B30M75 Printed in U S A Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9555 - 4 TL F 9555- 3 Unit Loading Fan Out 54F 74F Pin Names Description UL HIGH LOW Input IIH IIL Output IOH IOL OEAB OEBA CEAB CEBA LEAB LEBA A 0 - A7 B 0 - B7 A-to-B Output Enable Input (Active LOW) 10 10 20 m A b0 6 m A B-to-A Output Enable Input (Active LOW) 10 10 20 m A b0 6 m A A-to-B Enable Input (Active LOW) 10 20 20 m A b1 2 m A B-to-A Enable Input (Active LOW) 10 20...