MM54HC76 Datasheet PDF (Dual J-K Flip-Flops)

MM54HC76 - Dual J-K Flip-Flops

Description

These high speed (30 MHz minimum) J-K Flip-Flops utilize advanced silicon-gate CMOS technology to achieve the low power consumption and high noise immunity of standard CMOS integrated circuits along with the ability to drive 10 LS-TTL loads Each flip-flop has independent J K PRESET CLEAR and CLOCK i

Features

Y Y Y Y Y Typical propagation delay 16 ns Wide operating voltage range Low input current 1 mA maximum Low quiescent current 40 mA maximum (74HC Series) High output drive 10 LS-TTL loads Connection and Logic Diagrams Dual-In-Line Package Truth Table Inputs PR L H L H H H H H CLR H L L H H H H H CLK X X X J X X X L H L H X L X X X L L H H X Outputs Q Q v v v v H H L L H L L Q0 Q0 H L L H TOGGLE Q0 Q0 This is an unstable condition and is not guaranteed TL F 5074.
1 Top View Order.

Datasheet Details

Part number	MM54HC76
Manufacturer	National
File Size	136.21 KB
Description	Dual J-K Flip-Flops
Datasheet	MM54HC76 Datasheet
Additional preview pages of the MM54HC76 datasheet.

📁 Similar Datasheet

MM54HC73 - Dual J-K Flip-Flops (National Semiconductor)

MM54HC00 - Quad 2-Input NAND Gate (National Semiconductor)

MM54HC112 - Dual J-K Flip-Flop (National Semiconductor)

MM54HC133 - 13-Input NAND Gate (National Semiconductor)

MM54HC147 - 10-to-4 Line Priority Encoder (National Semiconductor)

MM54HC148 - 8-3 Line Priority Encoder (National Semiconductor)

MM54HC160 - Synchronous Binary Counter (National Semiconductor)

MM54HC161 - Synchronous Binary Counter (National Semiconductor)

MM54HC162 - Synchronous Binary Counter (National Semiconductor)

MM54HC163 - Synchronous Binary Counter (National Semiconductor)

Full PDF Text Transcription

Click to expand full text

MM54HC76 MM74HC76 Dual J-K Flip-Flops with Preset and Clear January 1988 MM54HC76 MM74HC76 Dual J-K Flip-Flops with Preset and Clear General Description These high speed (30 MHz minimum) J-K Flip-Flops utilize advanced silicon-gate CMOS technology to achieve the low power consumption and high noise immunity of standard CMOS integrated circuits along with the ability to drive 10 LS-TTL loads Each flip-flop has independent J K PRESET CLEAR and CLOCK inputs and Q and Q outputs These devices are edge sensitive to the clock input and change state on the negative going transition of the clock pulse Clear and preset are independent of the clock and accomplished by a low logic level on the corresponding input The 54HC 74HC logic family is functionally as well as pinout compatible with the standa

Published: May 9, 2005 |