Description
The NSBMC096 Burst Memory Controller is an integrated circuit which implements all aspects of DRAM control for high performance systems using an i960 CA CF SuperScalar Embedded Processor The NSBMC096 is functionally equivalent to the V96BMC TM The extremely high instruction rate achieved by these pr
Features
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Interfaces directly to the i960 CA Integrated Page Cache Management Manages Page Mode Dynamic Memory devices On-chip Memory Address Multiplexer Drivers Supports DRAMs trom 256 kB to 64 MB Bit counter timer Non-interleaved or two way interleaved operation 5-Bit Bus Watch Timer Software-configured operational parameters High-Speed Low Power CMOS technology
Block Diagram
TL V 11805.
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NSBMC096-16 Datasheet
