54AC169 Datasheet | National Semiconductor

Description The ’AC/’ACT169 is fully synchronous 4-stage up/down counter. The ’AC/’ACT169 is a modulo-16 binary counter. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the Clock. n n n n n n Synchronous counting and loading Built-In lookahead carry capability Presettable for programmable operation Outputs source/sink 24 m A ’ACT has TTL-patible inputs Standard Microcircuit Drawing (SMD) 5962-91603 Features n ICC reduced by 50% Logic Symbols Pin Names CEP CET CP P0- P3 PE U/D DS100276-1 Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Parallel Data Inputs Parallel Enable Input Up-Down Count Control Input Flip-Flop Outputs Terminal Count Output Q0- Q3 TC IEEE/IEC DS100276-2 FACT™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100276 .national. Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100276-3 DS100276-4 Logic Diagram DS100276-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Functional Description The ’AC/’ACT169 uses edge-triggered J-K-type flip-flops and have no constraints on changing the control or data input signals in either state of the Clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the remended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is LOW, the data on the P0- P3 inputs enters the flip-flops on the next rising edge of the Clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH;...