54AC373 Datasheet | National Semiconductor

Description The ’AC/’ACT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. Features n n n n n n ICC and IOZ reduced by 50% Eight latches in a single package TRI-STATE outputs for bus interfacing Outputs source/sink 24 m A ’ACT373 has TTL-patible inputs Standard Microcircuit Drawing (SMD) - ’AC373: 5962-87555 - ’ACT373: 5962-87556 Logic Symbols IEEE/IEC DS100329-1 DS100329-2 Pin Names D0- D7 LE OE O0- O7 Description Data Inputs Latch Enable Input Output Enable Input TRI-STATE Latch Outputs TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100329 .national. Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100329-4 DS100329-3 Functional Description The ’AC/’ACT373 contains eight D-type latches with TRI-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Truth Table Inputs LE X H H L OE H L L L Dn X L H X Outputs On Z L H O0 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial...