54ACTQ377 Datasheet | National Semiconductor

Description The ’ACQ ’ACTQ377 has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs The mon buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is low The register is fully edge-triggered The state of each D input one set-up time before the LOW-to-HIGH clock transition is transferred to the corresponding flip-flop’s Q output The CE input must be stable only one set-up time prior to the LOW-to-HIGH clock transition for predictable operation The ’ACQ ’ACTQ utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance FACT Quiet Series TM features GTOTM output control and undershoot corrector in addition to a split ground bus for superior performance Features Y ICC reduced by 50% Y...