54F533 Datasheet | National Semiconductor

Description The ’F533 consists of eight latches with TRI-STATE outputs for bus organized system applications The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH When LE is LOW the data that meets the setup times is latched Data appears on the bus when the Output Enable (OE) is LOW When OE is HIGH the bus output is in the high impedance state The ’F533 is the same as the ’F373 except that the outputs are inverted Features Eight latches in a single package TRI-STATE outputs for bus interfacing Inverted version of the ’F373 Guaranteed 4000V minimum ESD protection mercial 74F533PC Military Package Number N20A Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F533DM (Note 2) 74F533SC (Note 1) 74F533SJ (Note 1) 54F533FM (Note 2) 54F533LM (Note 2) Note 1 Devices also available in 13 J20A M20B M20D W20A E20A reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols IEEE IEC Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9548 - 3 TL F 9548- 4 TL F 9548 - 2 TL F 9548- 1 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9548 RRD-B30M75 Printed in U S A Unit Loading Fan Out 54F 74F Pin Names Description UL HIGH LOW 10 10 10 10 10 10 150 40 (33 3) Input IIH IIL Output IOH IOL 20 m A b0 6 m A 20 m A b0 6 m A 20 m A b0 6 m A b 3 m A 24 m A (20 m A) D0 - D7 LE OE O0 - O 7 Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) plementary TRI-STATE Outputs Function Table Inputs Output D H L X X O L H O0 Z LE H H L X OE L L L H H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Functional Description The ’F533 contains...