54F574 Datasheet | National Semiconductor

Description The ’F574 is a high-speed low power octal flip-flop with a buffered mon Clock (CP) and a buffered mon Output Enable (OE) The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP) transition This device is functionally identical to the ’F374 except for the pinouts Features Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Useful as input or output port for microprocessors Functionally identical to ’F374 TRI-STATE outputs for bus-oriented applications mercial 74F574PC Military Package Number N20A Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F574DM (Note 2) 74F574SC (Note 1) 74F574SJ (Note 1) 54F574FM (Note 2) 54F574LM (Note 2) J20A M20B M20D W20A E20A Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols IEEE IEC TL F 9567 - 1 TL F 9567 - 4 Unit Loading Fan Out 54F 74F Pin Names D0 - D7 CP OE O0 - O7 Description Data Inputs Clock Pulse Input (Active LOW) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Outputs UL HIGH LOW 10 10 10 10 10 10 150 40 (33 3) Input IIH IIL Output IOH IOL 20 m A b0 6 m A 20 m A b0 6 m A 20 m A b0 6 m A b 3 m A 24 m A (20 m A) TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9567 RRD-B30M75 Printed in U S A Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9567 - 3 TL F 9567- 2 Functional Description The ’F574 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs The buffered clock and buffered Output Enable are mon to all flip-flops The eight...