54LS173 Datasheet | National Semiconductor

Description This four-bit register contains D-type flip-flops with totempole TRI-STATE outputs capable of driving highly capacitive or low-impedance loads The high-impedance state and increased high-logic-level drive provide these flip-flops with the capability of driving the bus lines in a bus-organized system without need for interface or pull-up ponents Gated enable inputs are provided for controlling the entry of data into the flip-flops When both data-enable inputs are low data at the D inputs are loaded into their respective flipflops on the next positive transition of the buffered clock input Gate output control inputs are also provided When both are low the normal logic states of the four outputs are available for driving the loads or bus lines The outputs are disabled independently from the level of the clock by a high logic level at either output control input The outputs then present a high impedance and neither load nor drive the bus line Detailed operation is given in the truth table To minimize the possibility that two outputs will attempt to take a mon bus to opposite logic levels the output control circuitry is designed so that the average output disable times are shorter than the average output enable times Features Y TRI-STATE outputs interface directly with system bus Y Gated output control lines for enabling or disabling the outputs Y Fully independent clock eliminates restrictions for oper- ating in one of two modes Parallel load Do nothing (hold) Y For application as bus buffer registers Connection Diagram Function Table Dual-In-Line Package TL F 6403 - 1 Order Number 54LS173DMQB 54LS173FMQB 54LS173LMQB DM74LS173AM or DM74LS173AN See NS Package Number E20A J16A M16A N16E or W16A Inputs Clear Clock Data Enable G1 G2 Data D Output Q HX X L L X X X Q0 u L H X X Q0 u L X H X Q0 Lu L L L L Lu L When either M or N (or both) is (are) high the output is disabled to the high-impedance state however sequential operation of the...