54LS85 Datasheet | National Semiconductor

Description These 4-bit magnitude parators perform parison of straight binary or BCD codes Three fully-decoded decisions about two 4-bit words (A B) are made and are externally available at three outputs These devices are fully expandable to any number of bits without external gates Words of greater length may be pared by connecting parators in cascade The A l B A k B and A e B outputs of a stage handling less-significant bits are connected to the corresponding inputs of the next stage handling more-significant bits The stage handling the least-significant bits must have a high-level voltage applied to the A e B input The cascading path is implemented with only a two-gate-level delay to reduce overall parison times for long words Features Typical power dissipation 52 m W Typical delay (4-bit words) 24 ns Alternate Military Aerospace device (54LS85) is available Contact a National Semiconductor Sales Office Distributor for specifications Connection Diagram Dual-In-Line Package Function Table bs ol TL F 6379 - 1 paring Inputs A3 B3 A2 B2 X X A1 B1 X X X X A0 B0 X X X X X X A3 l B3 A3 k B3 e e e e e e e e e e e e et Cascading Inputs Ak B X X X X X X X X L H L X H L Outputs Ak B L H L H L H L H L H L L L H Al B X X X X X X X X H L L X H L Ae B X X X X X X X X L L H H L L Al B H L H L H L H L H L L L L H A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 A2 l B2 A2 k B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A1 l B1 A1 k B1 A1 e B1 A1 e B1 A1 e B1 A1 e B1 A1 e B1 A1 e B1 A1 e B1 A1 e B1 A0 l B0 A0 k B0 A0 e B0 A0 e B0 A0 e B0 A0 e B0 A0 e B0 A0 e B0 H e High Level L e Low Level X e Don’t Care C1995 National Semiconductor Corporation TL F 6379 e Order Number 54LS85DMQB 54LS85FMQB 54LS85LMQB DM54LS85J DM54LS85W DM74LS85M or DM74LS85N See NS Package Number E20A J16A M16A N16E or W16A Ae B L L L L L L L L L L H H L L RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note) If Military Aerospace...