74LS256 Datasheet | National Semiconductor

Description The ’LS256 is a dual 4-bit addressable latch with mon control inputs these include two Address inputs (A0 A1) an active LOW enable input (E) and an active LOW Clear input (CL) Each latch has a Data input (D) and four outputs (Q0 - Q3) When the Enable (E) is HIGH and the Clear input (CL) is LOW all outputs (Q0- Q3) are LOW Dual 4-channel demultiplexing occurs when the CL and E are both LOW When CL is HIGH and E is LOW the selected output (Q0 - Q3) determined by the Address inputs follows D When the E goes HIGH the contents of the latch are stored When operating in the addressable latch mode (E e LOW CL e HIGH) changing more than one bit of the Address (A0 A1) could impose a transient wrong address Therefore this should be done only while in the memory mode (E e CL e HIGH) Features Y Serial-to-parallel capability Y Output from each storage bit available Y Random (addressable) data entry Y Easily expandable Y Active low mon clear Connection Diagram Logic Symbol Dual-In-Line Package TL F 9823- 1 Order Number 54LS256DMQB 54LS256FMQB or DM74LS256N See NS Package Number J16A N16E or W16A VCC e Pin 16 GND e Pin 8 Pin Names A0 A1 Da Db E CL Q0a - Q3a Q0b - Q3b Description mon Address Inputs Data Inputs mon Enable Input (Active LOW) Conditional Clear Input (Active LOW) Side A Latch Outputs Side B Latch Outputs TL F 9823 - 2 C1995 National Semiconductor Corporation TL F 9823 RRD-B30M115 Printed in U S A Truth Table Inputs Outputs CL E A0...