ADC08161 Datasheet | National Semiconductor

Description Using a patented multi-step A/D conversion technique, the 8-bit ADC08161 CMOS A/D converter offers 500 ns conversion time, internal sample-and-hold (S/H), a 2.5V bandgap reference, and dissipates only 100 m W of power. The ADC08161 performs an 8-bit conversion with a 2-bit voltage estimator that generates the 2 MSBs and two low-resolution (3-bit) flashes that generate the 6 LBSs. Input signals are tracked and held by the input sampling circuitry, eliminating the need for an external sample-and-hold. The ADC08161 can perform accurate conversions of full-scale input signals at frequencies from DC to typically more than 300 k Hz (full power bandwidth) without the need of an external sample-and-hold (S/H). For ease of interface to microprocessors, this part has been designed to appear as a memory location or I/O port without the need for external interfacing logic. Key Specifications n n n n n n Resolution Conversion time (t CONV) Full power bandwidth Throughput rate Power dissipation Total unadjusted error 8 Bits 560 ns max (WR-RD Mode) 300 k Hz (typ) 1.5 MHz min 100 m W max ± 1⁄2 LSB and ± 1 LSB max Features n No external clock required n Analog input voltage range from GND to V+ n 2.5V bandgap reference Applications n n n n Mobile telemunications Hard-disk drives Instrumentation High-speed data acquisition systems Block Diagram DS011149-1 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS011149 .national. Connection Diagram RD Mode (logic low on the MODE pin) Wide-Body Small-Outline Package With CS low, a conversion starts on the falling edge of RD. Output data appears on DB0- DB7 at the end of conversion (Figures 1, 5). This is an active low output that indicates that a conversion is plete and the data is in the output latch. INT is reset by the rising edge of RD. This is the power supply ground pin. The ground pin should be connected to a “clean” ground reference point. These...