CD4031BC Datasheet | National Semiconductor

Description The CD4031BM CD4031BC is an integrated plementary MOS (CMOS) 64-stage fully static shift register Two data inputs DATA IN and RECIRCULATE IN and a MODE CONTROL input are provided Data at the DATA input (when MODE CONTROL is low) or data at the RECIRCULATE input (when MODE CONTROL is high) which meets the setup and hold time requirements is entered into the first stage of the register and is shifted one stage at each positive transition of the CLOCK Data output is available in both true and plement forms from the 64th stage Both the DATA OUT (Q) AND DATA OUT (Q) outputs are fully buffered The CLOCK input of the CD4031BM CD4031BC is fully buffered and present only a standard input load capacitance However a DELAYED CLOCK OUTPUT (CLD) has been provided to allow reduced clock drive fan-out and transition time requirements when cascading packages Features Wide supply voltage range High noise immunity Low power TTL patibility Fully static operation 3 0V to 15V 0 45 VDD (typ ) fan out of 2 driving 74L or 1 driving 74LS DC to 8 MHz VDD e 10V (typ ) Fully buffered clock input 5 p F (typ ) input capacitance Single phase clocking requirements Delayed clock output for reduced clock drive requirements Fully buffered outputs High current sinking capability 1 6 m A Q output VDD e 5V and 25 C Logic and Connection Diagrams TL F 5962 - 1 Dual-In-Line Package Order Number CD4031B Top View C1995 National Semiconductor Corporation TL F 5962 TL F 5962 - 2 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 and 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 5V to a 18V Supply Voltage (VDD) b 0 5V to VDD a 0 5V Input Voltage (VIN) b 65 C to a 150 C Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line 700 m W Small Outline 500 m W Lead Temp (TL) (Soldering 10 sec ) 260 C Remended Operating Conditions...