CD4724BM Datasheet | National Semiconductor

Description The CD4723B is a dual 4-bit addressable latch with mon control inputs including two address inputs (A0 A1) an active low enable input (E) and an active high clear input (CL) Each latch has a data input (D) and four outputs (Q0 - Q3) The CD4724B is an 8-bit addressable latch with three address inputs (A0- A2) an active low enable input (E) active high clear input (CL) a data input (D) and eight outputs (Q0 - Q7) Data is entered into a particular bit in the latch when that is addressed by the address inputs and the enable (E) is low Data entry is inhibited when enable (E) is high When clear (CL) and enable (E) are high all outputs are low When clear (CL) is high and enable (E) is low the channel demultiplexing occurs The bit that is addressed has an active output which follows the data input while all unaddressed bits are held low When operating in the addressable latch mode (E e CL e low) changing more than one bit of the address could impose a transient wrong address Therefore this should only be done while in the memory mode (E e high CL e low) Features Y Y Y Y Y Wide supply voltage range 3 0V to 15V High noise immunity 0 45 VDD (typ ) Low power TTL fan out of 2 driving 74L patibility or 1 driving 74LS Serial to parallel capability Storage register capability Random (addressable) data entry Active high demultiplexing capability mon active high clear Connection Diagrams CD4723B Dual-In-Line Package CD4724B Dual-In-Line Package Order Number CD4723B or CD4724B TL F 6003- 1 TL F 6003 - 2 Top View Top View Truth Table Mode Selection E L H L H CL L L H H Addressed Latch Follows Data Hold Previous Data Follows Data Reset to ‘0’’ Unaddressed Latch Holds Previous Data Holds Previous Data Reset to ‘‘0’’ Reset to ‘‘0’’ Mode Addressable Latch Memory Demultiplexer Clear C1995 National Semiconductor Corporation TL F 6003 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 2) If Military Aerospace specified devices are required please...