CGS74B303 Datasheet | National Semiconductor

Description These minimum skew clock drivers are designed for high frequency Clock Generation and Support (CGS) applications. These devices are ideal for duty cycle recovery applications with internal frequency divide-by-2 circuitry. The devices guarantee minimum output skew across the outputs of a given device. Skew parameters are also provided as a means to measure duty cycle requirements as those found in high speed clocking systems. Functional Description The CGS74B303 contains eight flip-flops designed to have low skew between outputs. The eight outputs (six in-phase with Cl K and two out-of-phase) toggle on successive Cl K a pulses. PRE and Cl R inputs are provided to set and Q outputs high or low independent of Cl K pin. Features - Clock Generation and Support (CGS) Devices ideal for high frequency signal generation or clock distribution applications - CGS74B version features National's Advanced Bipolar FASTTM l SI process - 1 ns pin-to-pin output skew - Specification for transition skew to meet duty cycle requirements - Current sourcing 24 m A and current sinking of 48 m A - low dynamic power consumption above 20 MHz - Guaranteed 4 k V ESD protection Ordering Code: See Section 5 Logic Diagram °1 Connection Diagrams Pin Assignment for DIP and s Ole Pin Assignment for 28- Pin pee He 05 He GHD GHD GHD He [Il][!QJIIl IIl IIl III(]] °6 (j] He [!] ~Il] He 1m °8 (j]] HC Ii] PRE 1m Os TLl F/l0966-3 TL/F/l0966-1 Pin Description Pin Names Cl K 01-0 8 PRE Cl R Description Clock Input Outputs Preset Clear [l1][ill Iil Illl- 1El1m e LK He Vee Vee Vee HC CLR TL/F/l0966-2 Truth Table Inputs Outputs CLR PRE el K 0 1-0 5 0 7-0 8...