CLC031A Datasheet | National Semiconductor

Description The CLC031A SMPTE 292M / 259M Digital Video Deserializer/Descrambler with Video and Ancillary Data FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial ponent video data, to 20-bit parallel data with a synchronized parallel word-rate clock. It also deserializes and decodes SMPTE 259M, 270Mbps, 360Mbps and SMPTE 344M (proposed) 540Mbps serial ponent video data, to 10-bit parallel data. Functions performed by the CLC031A include: clock/data recovery from the serial data, serial-to-parallel data conversion, SMPTE standard data decoding, NRZI-to-NRZ conversion, parallel data clock generation, word framing, CRC and EDH data checking and handling, Ancillary Data extraction and automatic video format determination. The parallel video output features a variabledepth FIFO which can be adjusted to delay the output data up to 4 parallel data clock periods. Ancillary Data may be selectively extracted from the parallel data through the use of masking and control bits in the configuration and control registers and stored in the on-chip FIFO. Reverse LSB dithering is also implemented. The unique multi-functional I/O port of the CLC031A provides external access to functions and data stored in the configuration and control registers. This feature allows the designer greater flexibility in tailoring the CLC031A to the desired application. The CLC031A is auto-configured to a default operating condition at power-on or after a reset mand. Separate power pins for the PLL, deserializer and other functional circuits improve power supply rejection and noise performance. The CLC031A has a unique Built-In Self-Test (BIST) and video Test Pattern Generator (TPG). The BIST enables prehensive testing of the device by the user. The BIST uses the TPG as input data and includes SD and HD ponent video test patterns, reference black, PLL and EQ pathologicals and a 75% saturation, 8 vertical colour bar pattern, for all...