CLC949 Datasheet | National Semiconductor

Description The linear CLC949 is a 12-bit analog-to-digital converter subsystem including 12-bit quantizer, sample-and-hold amplifier, and internal reference. The CLC949 has been optimized for low power operation with high dynamic range. The CLC949 has a unique feature which allows the user to adjust internal bias levels in the converter which results in a trade-off between power dissipation and maximum conversion rate. With bias set for 220m W power dissipation the converter operates at 20MSPS. Under these conditions, dynamic performance with a 9.9MHz analog input is typically 68d B SNR and 72d Bc SFDR. When bias is set for only 65m W power dissipation the converter maintains excellent performance at 5MSPS. With a 2.4MHz analog input signal the SNR is 70d B and SFDR is 78d Bc. This excellent dynamic performance in the frequency domain without high power requirements make the part a strong performer for munications and radar applications. The low input noise of the CLC949, its 0.5LSB differential linearity error specification, fast settling, and low power dissipation also lead to excellent performance in imaging systems. All parts are thoroughly tested to insure that guaranteed specifications are met. The CLC949 incorporates an input sample-and-hold amplifier followed by a quantizer which uses a pipelined architecture to minimize parator count and the associated power dissipation penalty. An on-board voltage reference is provided. Analog input signals, conversion clock, and a single supply are all that are required for CLC949 operation. The CLC949 exhibits very stable performance over the mercial and industrial temperature ranges. Most parameters shift very little as the ambient temperature changes from -40°C to 85°C. An exception to this rule is the dynamic performance of the converter. As the temperature is increased, the distortion increases, especially at higher input frequencies. This can be seen in the plot on page 3. For input frequencies below 7MHz, there is...