DM54191 Datasheet | National Semiconductor

Description This circuit is a synchronous reversible up down counter The 191 is a 4-bit binary counter Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change simultaneously when so instructed by the steering logic This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters The outputs of the four master-slave flip-flops are triggered on a low-to-high level transition of the clock input if the enable input is low A high at the enable input inhibits counting Level changes at either the enable input or the down up input should be made only when the clock input is high The direction of the count is determined by the level of the down up input When low the counter counts up and when high it...