DM54L73 Datasheet | National Semiconductor

Description This device contains two independent positive pulse triggered J-K flip-flops with plementary outputs The J and K data is processed by the flip-flops after a plete clock pulse While the clock is low the slave is isolated from the master On the positive transition of the clock the data from the J and K inputs is transferred to the master While the clock is high the data from the J and K inputs are disabled On the negative transition of the clock the data from the master is transferred to the slave The logic states of the J and K inputs must not be allowed to change while the clock is high Data is transferred to the outputs on the falling edge of the clock pulse A low logic level on the clear input will reset the outputs regardless of the logic states of the other inputs Connection Diagram Dual-In-Line Package TL F 6630 - 1 Order Number DM54L73J or DM54L73W See NS Package Number J14A or W14B Function Table Inputs CLR L H H H H CLK X J X L H L H K X L L H H Outputs Q Q L H QO QO H L L H Toggle H e High Logic Level X e Either Low or High Logic Level L e Low Logic Level e Positive pulse data The J and K inputs must be held constant while the clock is high Data is transferred to the outputs on the falling edge of the clock pulse QO e The output logic level before the indicated input conditions were established Toggle e Each output changes to the plement of its previous level on each plete high level clock pulse C1995 National Semiconductor Corporation TL F 6630 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage Input Voltage Storage Temperature Range 8V 5 5V Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device can not be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical...