DM74LS90N Datasheet | National Semiconductor

Description Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the count cycle length is divide-by-five for the DM74LS90. All of these counters have a gated zero reset and the DM74LS90 also has gated set-to-nine inputs for use in BCD nine’s plement applications. To use their maximum count length (decade or four bit binary), the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are as described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained from the DM74LS90 counters by connecting the QD output to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output QA. Features s Typical power dissipation 45 m W s Count frequency 42 MHz Ordering Code: Order Number Package Number Package Description DM74LS90M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Reset/Count Truth Table R0(1) H H X X L L X Reset Inputs R0(2) R9(1) R9(2) X L H L X L X Output QD QC QB QA LLLL LLLL HL LH COUNT COUNT COUNT COUNT © 2000 Fairchild Semiconductor Corporation DS006381 .fairchildsemi. DM74LS90 Function...