DP83222 Datasheet | National Semiconductor

Description The DP83222 CYCLONE Stream Cipher Scrambler Descrambler Device is an integrated circuit designed to interface directly with the serial bit streams of a Twisted Pair FDDI PMD The DP83222 is designed to be fully patible with the National Semiconductor FDDI Chip Sets including the DP83223 TWISTERTM (Twisted Pair Transceiver) The DP83222 requires a 125 MHz Transmit Clock and corresponding Receive Clock for synchronous data scrambling and descrambling The DP83222 is pliant with the ANSI X3T9 5 TP-PMD draft standard and is required for the reduction of EMI emission over unshielded media The DP83222 is specified to work in conjunction with existing twisted pair transceiver signalling schemes such as MLT-3 or NRZI and enables high bandwidth transmission over Twisted Pair copper media Features Y Y Y Y Y Y Y Enables 100 Mbps FDDI signalling over Category 5 Unshielded Twisted Pair (UTP) cable and Type 1 Shielded Twisted Pair (STP) Reduces EMI emissions over Twisted Pair media patible with ANSI X3T9 5 TP-PMD Standard Requires a single a 5V supply Transparent mode of operation Flexible NRZ and NRZI format options Advanced Bi CMOS process Signal Detect and Clock Detect inputs provided for enhanced functionality Suitable for Fiber Optic PMD replacement applications Block Diagram TL F 11885 - 1 FIGURE 1 DP83222 Block Diagram CYCLONETM CDDTM CDLTM PLAYERTM PLAYER a TM and TWISTERTM are trademarks of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 11885 RRD-B30M105 Printed in U S A 1 0 Functional Description 1 1 OVERVIEW The DP83222 Stream Cipher Scrambler Descrambler Device consists of 7 major functional blocks as shown in Figure 1 The Scrambler section is prised of an Encoder a Decoder a linear Feedback Shift Register with support gates and the Control Logic block The Decoder accepts synchronous differential clock and data (data can be either NRZ or NRZI formatted) from the Physical Layer and delivers NRZ data to the 11-bit...