DP83223 Datasheet | National Semiconductor

Description The DP83223 Twisted Pair Transceiver is an integrated circuit capable of driving and receiving three-level (MLT-3) encoded datastreams. The DP83223 Transceiver is designed to interface directly with National Semiconductor’s Fast Ethernet and FDDI Chip Sets or similar Physical Layer silicon allowing low cost data links over copper based media. The DP83223 allows links of up to 100 meters over Shielded Twisted Pair (Type-1A STP) and Category-5 datagrade Unshielded Twisted Pair (Cat-5 UTP) or equivalent. The DP83223 is available in a 28 pin PLCC package and a 32 pin PQFP package. Features s s s s s s s s s patible with ANSI X3.263 TP-PMD draft standard Allows use of Type 1 STP and Category 5 UTP cables Requires a single +5V supply Integrated transmitter and receiver with adaptive equalization circuit Isolated TX and RX power supplies for minimum noise coupling Loopback feature for board diagnostics Digitally Synthesized transmit signal transition time control for reduced EMI Programmable transmit voltage amplitude Suitable for 100BASE-TX Fast Ethernet and Twisted Pair FDDI applications System Connection Diagrams DP83257VF or DP83256VF-AP PLAYER+ TX DATA Descrambled RX DATA Recovered RXDATA DP83840A 10/100 Ethernet PHY Phased RX CLOCK Recovered RXCLOCK RX DATA DP83222 Stream Cipher Scrambled TX DATA Scrambled RX DATA Signal Detect SIGDET Scrambled TX DATA DP83223 Transceiver PMD Encoded TXDATA PMD Encoded RXDATA DP83223 Transceiver PMD Encoded TXDATA PMD Encoded RXDATA Magnetics Magnetics Twisted Pair Media Twisted Pair Media 100BASE-TX © 1997 National Semiconductor Corporation Twisted Pair FDDI General Description (Continued) Table of Contents 1.0 2.0 3.0 Connection Diagram Pin Description Functional Description 3.1 Overview 3.2 MLT-3 Encoding 3.3 Transition Time Control 3.4 Adaptive Equalization 3.5 Jitter Performance DC and AC Specifications 4.1 TRANSMIT TIMING 4.2 RECEIVE PROPAGATION DELAY 4.3 LOOPBACK PROPAGATION DELAY...