DP83255 Datasheet | National Semiconductor

Description The DP83251 DP83255 PLAYER device implements one Physical Layer (PHY) entity as defined by the Fiber Distributed Data Interface (FDDI) ANSI X3T9 5 Standard The PLAYER device contains NRZ NRZI and 4B 5B encoders and decoders serializer deserializer framing logic elasticity buffer line state detector generator link error detector repeat filter smoother and configuration switch Features Y Y Y Y Y Y Y Y Y Low power CMOS-BIPOLAR process Single 5V supply Full duplex operation Separate management interface (Control Bus) Parity on PHY-MAC Interface and Control Bus Interface On-chip configuration switch Internal and external loopback DP83251 for single attach stations DP83255 for dual attach stations TL F 10386 - 1 FIGURE 1-1 FDDI Chip Set Block Diagram TRI-STATE is a registered trademark of National Semiconductor Corporation BSITM BMACTM PLAYERTM CDDTM and CRDTM are trademarks of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 10386 RRD-B30M105 Printed in U S A Table of Contents 10 20 FDDI CHIP SET OVERVIEW 70 ELECTRICAL CHARACTERISTICS ARCHITECTURE DESCRIPTION 2 1 Overview 2 2 Interfaces 3 0 FUNCTIONAL DESCRIPTION 3 1 Receiver Block 3 2 Transmitter Block 3 3 Configuration Switch 4 0 MODES OF OPERATION 4 1 Run Mode 4 2 Stop Mode 4 3 Loopback Mode 4 4 Cascade Mode 5 0 REGISTERS 6 0 PIN DESCRIPTIONS 6 1 DP83251 6 2 DP83255 7 1 Absolute Maximum Ratings 7 2 Remended Operating Conditions 7 3 DC Electrical Charcteristics 7 4 AC Electrical Charcteristics 7 5 Test Circuits 8 0 DETAILED DESCRIPTIONS 8 1 Framing Hold Rules 8 2 Noise Events 8 3 Link Errors 8 4 Repeat Filter 8 5 Smoother 8 6 National Byte-wide Code for PHY-MAC Interface 1 0 FDDI Chip Set Overview National Semiconductor’s FDDI chip set consists of five ponents as shown in Figure 1-1 For more information on the other devices of the chip set consult the appropriate datasheets and application notes DP83231 CRD TM Device Clock Recovery Device The Clock Recovery Device...