DP8406 Datasheet | National Semiconductor

Description The DP8406 device is a 32-bit parallel error detection and correction circuit (EDAC) in a 52-pin or 68-pin package The EDAC uses a modified Hamming code to generate a 7-bit check word from a 32-bit data word This check word is stored along with the data word during the memory write cycle During the memory read cycle the 39-bit words from memory are processed by the EDAC to determine if errors have occurred in memory Single-bit errors in the 32-bit data word are flagged and corrected Single-bit errors in the 7-bit check word are flagged and the CPU sends the EDAC through the correction cycle even though the 32-bit data word is not in error The correction cycle will simply pass along the original 32-bit data word in this case and produce error syndrome bits to pinpoint the error-generating location Dual-bit errors are flagged but not corrected These errors may occur in any two bits of the 39-bit word from memory (two errors in the 32-bit data word two errors in the 7-bit check word or one error in each word) The gross-error condition of all LOWs or all HIGHs from memory will be detected Otherwise errors in three or more bits of the 39-bit word are beyond the capabilities of these devices to detect Read-modify-write (byte-control) operations can be performed by using output latch enable LEDBO and the individual OEB0 through OEB3 byte control pins Diagnostics are performed on the EDACs by controls and internal paths that allow the user to read the contents of the Data Bit and Check Bit input latches These will determine if the failure occurred in memory or in the EDAC Features Y Y Y Y Y Y Y Detects and corrects single-bit errors Detects and flags dual-bit errors Built-in diagnostic capability Fast write and read cycle processing times Byte-write capability Guaranteed 4000V minimum ESD protection Fully pin and function patible with SN74ALS632A thru SN74ALS635 series TI’s Simplified Functional Block TL F 9579 - 9 Device DP8406 DP8406 Package 52-Pin...