DS08MB200 Datasheet | National Semiconductor

Description The DS08MB200 is a dual-port 1 to 2 repeater/buffer and 2 to 1 multiplexer. High-speed data paths and flow-through pinout minimize internal device jitter and simplify board layout. The differential inputs and outputs interface to LVDS or Bus LVDS signals such as those on National’s 10-, 16-, and 18- bit Bus LVDS Ser Des, or to CML or LVPECL signals. The 3.3V supply, CMOS process, and robust I/O ensure high performance at low power over the entire industrial -40 to +85˚C temperature range. Features n Up to 800 Mbps data rate per channel n LVDS/BLVDS/CML/LVPECL patible inputs, LVDS patible outputs n Low output skew and jitter n On-chip 100Ω input termination n 15 k V ESD protection on LVDS Inputs/Outputs n Hot plug Protection n Single 3.3V supply n Industrial -40 to +85˚C temperature range n 48-pin LLP Package Typical Application Block Diagram FIGURE 1. DS08MB200 Block Diagram © 2006 National Semiconductor Corporation DS201574 .national. Data Sheet 4 U . .. Pin Descriptions Pin Name SIA_0+ SIA_0- SIA_1+ SIA_1- SIB_0+ SIB_0- SIB_1+ SIB_1- LI_0+ LI_0- LI_1+ LI_1- SOA_0+ SOA_0- SOA_1+ SOA_1- SOB_0+ SOB_0- SOB_1+ SOB_1- LO_0+ LO_0- LO_1+ LO_1- MUX_S0 MUX_S1 ENA_0 ENA_1 ENB_0 ENB_1 ENL_0 ENL_1 POWER VDD GND 6, 12, 37, 43, 48 2, 3, 46, 47 (Note 2) 1, 5, 23, 24, 25, 26, 44 I, Power I, Power VDD = 3.3V ± 0.3V. Ground reference for LVDS and CMOS circuitry. For the LLP package, the DAP is used as the primary GND connection to the device. The DAP is the exposed metal contact at the bottom of the LLP-48 package. It should be connected to the ground plane with at least 4 vias for optimal AC and thermal performance. No Connect LLP Pin Number 30 29 19 20 28 27 21 22 40 39 9 10 34 33 15 16 32 31 17 18 42 41 7 8 38 11 36 13 35 14 45 4 I/O, Type Description SWITCH SIDE DIFFERENTIAL INPUTS I, LVDS I, LVDS I, LVDS I, LVDS Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL patible....