DS90C032B Datasheet | National Semiconductor

Description The DS90C032B is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90C032B accepts low voltage (350 m V) differential input signals and translates them to CMOS (TTL patible) output levels. The receiver supports a TRI-STATE® function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions. The DS90C032Bprovides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present. The DS90C032Band panion line driver (DS90C031B) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications. Features n >155.5 Mbps (77.7 MHz) switching rates n Accepts small swing (350 m V) differential signal levels n High Impedance LVDS inputs with power down n Ultra low power dissipation n 600 ps maximum differential skew (5V, 25˚C) n 6.0 ns maximum propagation delay n Industrial operating temperature range n Available in surface mount packaging (SOIC) n Pin patible with DS26C32A, MB570 (PECL) and 41LF (PECL) n Supports OPEN and terminated input failsafe n Conforms to ANSI/TIA/EIA-644 LVDS standard Connection Diagram Dual-In-Line Functional Diagram Order Number DS90C032BTM See NS Package Number M16A Receiver Truth Table ENABLES EN EN- LH All other binations of ENABLE inputs TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2003 National Semiconductor Corporation DS100990 INPUTS RIN+ - RIN- X VID ≥ 0.1V VID ≤ - 0.1V Failsafe OPEN or Terminated OUTPUT ROUT Z H .national. Absolute Maximum Ratings (Note 1) If...