DS90C383A Datasheet | National Semiconductor

Description The DS90C383A/DS90CF383A transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 227 Mbytes/ sec. The DS90C383A transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. The DS90CF383A is fixed as a Falling edge strobe transmitter. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF384) without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. 2.0 Features n 20 to 65 MHz shift clock support n Rejects > ± 3ns Jitter from VGA chip with less than 225ps output Jitter @65MHz (TJCC) n Best- in- Class Set & Hold Times on Tx INPUTs n Tx power consumption < 130 m W (typ) @65MHz Grayscale n > 50% Less Power Dissipation than Bi CMOS Alternatives n Tx Power-down mode < 200µW (max) n ESD rating > 7 k V (HBM), > 500V (EIAJ) n Supports VGA, SVGA, XGA and Dual Pixel SXGA. n Narrow bus reduces cable size and cost n Up to 1.8 Gbps throughput n Up to 227 Megabytes/sec bandwidth n 345 m V (typ) swing LVDS devices for low EMI n PLL requires no external ponents n patible with TIA/EIA-644 LVDS standard n Low profile 56-lead TSSOP package n Improved replacement for: SN75LVDS83 - DS90C383A SN75LVDS81 - DS90CF383A 3.0 Block Diagrams DS90C383A/DS90CF383A DS100100-1 Order Number DS90C383AMTD or DS90CF383AMTD See NS Package Number MTD56 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999...