DS90C385 Datasheet | National Semiconductor

Description The DS90C385 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 297.5 Mbytes/sec. Also available is the DS90C365 that converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. Both transmitters can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF386/ DS90CF366) without any translation logic. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. Features n 20 to 85 MHz shift clock support n Best- in- Class Set & Hold Times on Tx INPUTs n Tx power consumption < 130 m W (typ) @85MHz Grayscale n Tx Power-down mode < 200µW (max) n Supports VGA, SVGA, XGA and Single/Dual Pixel SXGA. n Narrow bus reduces cable size and cost n Up to 2.38 Gbps throughput n Up to 297.5 Megabytes/sec bandwidth n 345 m V (typ) swing LVDS devices for low EMI n PLL requires no external ponents n patible with TIA/EIA-644 LVDS standard n Low profile 56-lead or 48-lead TSSOP package Block Diagrams DS90C385 DS90C365 DS100868-1 DS100868-29 Order Number DS90C385MTD See NS Package Number MTD56 Order Number DS90C365MTD See NS Package Number MTD48 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100868 .national. Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are...