DS90CR217 Datasheet | National Semiconductor

Description The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR218 receiver converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 75 MHz, 21 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel. Using a 75 MHz clock, the data throughput is 1.575 Gbit/s (197 Mbytes/sec). This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. Features n 20 to 75 MHz shift clock support n 50% duty cycle on receiver output clock n Best- in- Class Set & Hold Times on Tx INPUTs and Rx OUTPUTs n Low power consumption n Tx + Rx Power-down mode < 400µW (max) n ± 1V mon mode range (around +1.2V) n Narrow bus reduces cable size and cost n Up to 1.575 Gbps throughput n Up to 197 Megabytes/sec bandwidth n 345 m V (typ) swing LVDS devices for low EMI n PLL requires no external ponents n Rising edge data strobe n patible with TIA/EIA-644 LVDS standard n Low profile 48-lead TSSOP package Block Diagrams DS90CR217 DS90CR218 DS100871-1 DS100871-27 Order Number DS90CR217MTD See NS Package Number MTD48 Order Number DS90CR218MTD See NS Package Number MTD48 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100871 .national. DS90CR217/DS90CR218 Pin Diagrams DS100871-21 DS100871-22 DS90CR218 Typical Application DS100871-23 .national. DS90CR217/DS90CR218 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) - 0.3V to +4V CMOS/TTL Input Voltage -...