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DS90CR217 - +3.3V Rising Edge Data Strobe LVDS

General Description

The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link.

Key Features

  • 1.
  • 2 20 to 85 MHz Shift Clock Support.
  • 50% Duty Cycle on Receiver Output Clock.
  • Best-in-Class Set & Hold Times on TxINPUTs.
  • Low Power Consumption.
  • ±1V Common-Mode Range (Around +1.2V).
  • Narrow Bus Reduces Cable Size and Cost.
  • Up to 1.785 Gbps Throughput.
  • Up to 223 Mbytes/sec Bandwidth.
  • 345 mV (typ) Swing LVDS Devices for Low EMI.
  • PLL Requires No External Components.
  • Rising Edge Data Strobe.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DS90CR217 www.ti.com SNLS226A – OCTOBER 2006 – REVISED FEBRUARY 2013 DS90CR217 +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz Check for Samples: DS90CR217 FEATURES 1 •2 20 to 85 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best-in-Class Set & Hold Times on TxINPUTs • Low Power Consumption • ±1V Common-Mode Range (Around +1.2V) • Narrow Bus Reduces Cable Size and Cost • Up to 1.