DS90CR281 Datasheet | National Semiconductor

Description The DS90CR281 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR282 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 40 MHz, 28 bits of TTL data are transmitted at a rate of 280 Mbps per LVDS data channel. Using a 40 MHz clock, the data throughput is 1.12 Gbit/s (140 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 28-bit wide data bus and one clock, up to 58 conductors are required. With the Channel Link chipset as few as 11 conductors (4 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables’ smaller form factor. The 28 CMOS/TTL inputs can support a variety of signal binations. For example, 7 4-bit nibbles or 3 9-bit (byte + parity) and 1 control. Features n n n n n n n n Narrow bus reduces cable size and cost ± 1V mon mode range (ground shifting) 290 m V swing LVDS data transmission 1.12 Gbit/s data throughput Low swing differential current mode drivers reduce EMI Rising edge data strobe Power down mode Offered in low profile 56-lead TSSOP package Block Diagrams DS90CR281 DS90CR282 DS012638-27 DS012638-1 Order Number DS90CR281MTD See NS Package Number MTD56 Order Number DS90CR282MTD See NS Package Number MTD56 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS012638 .nationa...