DS90UR124 Datasheet | National Semiconductor

Description The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. The DS90UR241/124 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range EMI is further reduced. In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. Using National Semiconductor’s proprietary random lock, the Serializer’s parallel data are randomized to the Deserializer without the need of REFCLK. n Supports AC-coupling data transmission n Individual power-down controls for both Transmitter and Receiver n 1.8V VCM at LVDS input side n Embedded clock CDR (clock and data recovery) on Receiver and no source of reference clock needed n All codes RDL (random data lock) to support hot-pluggable applications n LOCK output flag to ensure data integrity at Receiver side n Balanced TSETUP/THOLD between RCLK and RDATA on Receiver side n Adjustable PTO (progressive turn-on) LVCMOS outputs on Receiver to minimize EMI and SSO effects n @Speed BIST to validate link integrity n All LVCMOS inputs and control pins have internal pulldown n On-chip filters for PLLs on Transmitter and Receiver n 48-pin TQFP package for Transmitter and 64-pin TQFP package for Receiver n Pure CMOS .35 µm process n Power supply range 3.3V ± 10% n Temperature range - 40˚C to +105˚C n Greater than 8 k V HBM ESD structure n Meets ISO 10605 ESD pliance n...