LM2502 Datasheet | National Semiconductor

Description The LM2502 device is a dual link display interface SERDES that adapts existing CPU / video busses to a low power current-mode serial MPL link. The chipset may also be used for a RGB565 application with glue logic. The interconnect is reduced from 22 signals to only 3 active signals with the LM2502 chipset easing flex interconnect design, size and cost. The Master Serializer (SER) resides beside an application processor or baseband processor and translates a parallel bus from LVCMOS levels to serial MPL levels for transmission over a flex cable and PCB traces to the Slave Deserializer (DES) located near the display module. Dual display support is provided for a primary and sub display through the use of two Chip Select signals. A Mode pin selects either a i80 or m68 style interface. The Power_Down (PD- ) input controls the power state of the MPL interface. When PD- is asserted, the MD1/0 and MC signals are powered down to save current. The LM2502 implements the physical layer of the MPL Standard (MPL-0). The LM2502 is offered in NOPB (Lead-free) UFBGA and LLP packages. Features n n n n n n n n n n n n > 300 Mbps Dual Link Raw Throughput MPL Physical Layer (MPL-0) Pin selectable Master / Slave mode Frequency Reference Transport plete LVCMOS / MPL Translation Interface Modes: - 16-bit CPU, i80 or m68 style - RGB565 with glue logic - 30˚C to 85˚C Operating Range Link power down mode reduces IDDZ < 10 µA Dual Display Support (CS1- & CS2- ) Via-less MPL interconnect feature 3.0V Supply Voltage (VDD and VDDA) Interfaces to 1.7V to 3.3V Logic (VDDIO) System Benefits n n n n n Small Interface Low Power Low EMI Frequency Reference Transport Intrinsic Level Translation Typical Application Diagram Ordering Information NSID LM2502SM LM2502SQ Package Type 49 Lead UFBGA style, 4.0 X 4.0 X 1.0 mm, 0.5 mm pitch 1000 std reel, LM2502SMX 4500 reel 40 Lead LLP style, 5.0 X 5.0 X 0.8 mm, 0.4 mm pitch 1000 std reel, LM2502SQX 4500 reel Package ID SLH49A SQF40A ©...